Advanced Methodology for Assessing CPI-Induced Stress Effects on Chip Performance and Reliability

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#reliability #photonics #electronics #advanced packaging #heterogeneous integration #EDA

(22:56) - Valeriy Sukharev, Siemens EDA

The talk presents a multiscale simulation methodology and EDA tool that assesses the effect of thermal mechanical stresses arising after die assembly on chip performance and reliability. Existing non-uniformities of feature geometries and composite nature of on-chip interconnect layers are addressed by developed methodology of the anisotropic effective thermomechanical material properties (EMP) that reduces complexity of FEA simulations and enhances the accuracy and performance. The physical nature of the calculated EMP makes it scalable with the simulation grid size, which enables resolution of stress/strain at different scales from package to device channel. With feature-scale resolution, the tool enables accurate calculation of stress components in the active region of each device, where the carrier mobility variation results in deviations of circuits performance. The tool’s capability of back-annotation of the hierarchic SPICE netlist with the stress values allows a user to perform circuit simulation in different stress environments, by placing the circuit block in different locations in the layout characterized by different distances from the stress sources, such as die edges and C4 bumps. Both schematic and post-layout netlists can be employed for finding optimal floorplan minimizing the stress impact at early design stages, as well as for the final design sign-off. Electrical measurements on a specially designed test-package were used for validation of the methodology. The study demonstrates that the developed electronic design automation (EDA) tool and methodology can be used for accurate warpage prediction in different types of IC stacks at an early stage of package design.

Valeriy Sukharev is a Technical Lead at the Design to Silicon Division (Calibre) of Siemens EDA (former Mentor Graphics). He is a holder of the Ph.D. degree in physical chemistry from the Russian Academy of sciences. Prior to Mentor Graphics, Dr. Sukharev was a Chief Scientist with Ponte Solutions, Inc., a Visiting Professor with Brown University, and a Guest Researcher with NIST, Gaithersburg, MD. He also held senior technical positions with LSI Logic Advanced Development Lab.
Dr. Sukharev's major research activity is in the development of new full-chip modeling and simulation capabilities for the EDA, semiconductor processing and reliability management. He has authored/co-authored more than 150 publications in scientific journals and conference proceedings and holds 20 plus U.S. patents. He has co-authored and co-edited 5 books. He serves on the Editorial Boards and technical/steering committees of a number of profiling journals and conferences. He was a recipient of multiple Mahboob Khan Outstanding Industry Liaison/Associate Awards (SRC) and multiple best paper awards from ICCAD.

For videos/slides from other talks at the Symposium on Reliability of Electronics and Photonics Packaging (REPP'22), please visit our website and join our IEEE Dlist:  attend.ieee.org/repp

 

(22:56) - Valeriy Sukharev, Siemens EDA

The talk presents a multiscale simulation methodology and EDA tool that assesses the effect of thermal mechanical stresses arising after die assembly on chip performance and reliability. Existing non-uniformities of feature geometries and composite nature of on-chip interconnect layers are addressed by developed methodology of the anisotropic effective thermomechanical material properties (EMP) that reduces complexity of FEA simulations and enhances the accuracy and performance. The physical nature of the calculated EMP ....

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