A 3D Heterogenous Integration Future: Enabling Continued Scaling of Electronics Systems

(51:10 +Q&A)   A detailed view of computer system chip packaging, from single-chip packages to 2-D and 3-D heterogeneous integration and chiplets, as presented at the Electronics Packaging Society's one-day Workshop as part of SEMICON/West in San Francisco.  This is a great overview by IMEC's VP of R&D.
Dr Eric Beyne, IMEC, received the Degree in Electrical Engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986 he has been with IMEC in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies. Currently, he is an IMEC fellow, VP of R&D, and Program Director of imec’s 3D System Integration program.

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